The present invention relates to a dynamic random access memory device (DRAM). More specifically the invention relates to a DRAM with increased process speed.
FIG. 13 is a block diagram of the conventional 4 Mbits DRAM formed with four 1 Mbits memory cell arrays. The 4 Mbits DRAM includes memory cell arrays 100, 110, 120 and 130 in a matrix form of 4000 bits.times.256 rows. Row decoders 102, 112, 122 and 132, sense amplifiers 103, 113, 123 and 133 for amplification and refreshing of read out data of the memory cells, and column decoders 104, 114, 124 and 134 are provided corresponding to respective of these memory cell arrays. Also, a block decoder 140 is provided for performing selection of respective of the memory cell arrays. The block decoder, the row decoder and the column decoder generate decoded outputs in response to 10 bits address signal ADO.about.AD9. Furthermore, a refresh, R/W controller 141 is provided for generating timing signals (RAS, CAS, WE, OE) necessary for respective of reading, writing and reflecting operations.
In this DRAM, the data bits held in each memory cell are regularly or periodically refreshed. Assuming that the memory cell arrays to be refreshed at one refreshing operation is 1 block, the 4 Mbits DRAM is refreshed per each memory cell arrays 100, 110, 120 and 130. Since each block is 4000 bits.times.256 rows, the refreshing operation will be completed by 1024 times of refreshing operation for a unit of 4 Kbits.
Constructions of the sense amplifier 103 and the column decoder 104 connected to a pair of digit lines D, and CD are shown in FIG. 14. Memory cells are connected to respective of junctions of word lines W0.about.W255 and the pair of digit lines D and CD. The pair of digit lines D and CD are enabled to be precharged by providing an equal potential by means of a precharge transistor 1 which is activated through a precharge line PRC.
The sense amplifier 103 is in a form of a differential amplifier with C-MOS transistors. The active state and inactive state of this sense amplifier is controlled by activation lines SAP and SAN. The sense amplifier is activated by supplying a power source level to the line SAP and a grounding level to the line SAN. On the other hand, the sense amplifier is deactivated by supplying an intermediate level for both lines. The column decoder 104 is designed to supply an amplified data of the sense amplifier 103 to a data bus I/O by supplying the power source level to a column selection line YSW.
FIG. 15 shows signal waveforms at major portions in the circuits of FIGS. 13 and 14. Before access, the pair of digit lines C and CD are held at the equal level by precharge of the transistor I due to high level at the precharge line PRC. After initiation of access (time t.sub.1), the activation lines SAP and SAN respectively become the power source level and the ground level to activate the sense amplifier 103. Then, the word line W0 is selected and thus the power source level is supplied thereto. According to cell data on this word line W0, the pair of digit lines D and CD are driven. Subsequently, the column selection line YSW of the column decoder 104 becomes the power source level (time t.sub.2). Then, the data on the pair of digit lines C and CD is transferred to a pair of data bus I/O. After completion of access, all of the activation lines SAP and SAN and the digit lines C and CD become equal level. Then, the sense amplifier 103 returns into the inactive state.
Substantially the same process of operations to the above-mentioned reading out operation takes place in a refreshing operation.
The conventional DRAM as set forth above includes high speed access modes, such as a page mode, static column mode or so forth. However, such high speed access is only effective for the data present in the activated sense amplifier upon activation of the sense amplifier even though the data in all of the memory cells connected to the word line are read out in response to rising of the potential at the word line. Once the access is completed, the data is not saved so that the next access has to be again initiated from selection of the word line. In addition, associated with increasing of the capacity of the DRAM, it is becoming impossible to activate overall sense amplifiers. In practice, in case of the DRAM of 4 Mbits, only one fourth of the sense amplifier can be activated at one time. Accordingly, data to be accessed in the high speed access mode, such as page mode, static column mode or so forth is limited to those held by the activated sense amplifiers which are one fourth of the overall sense amplifiers.
Discussing about the example of FIG. 13, when the sense amplifier 103 is activated, remaining sense amplifiers 113, 123 and 133 are held at inactive state and thus not maintaining data. Also, since the block address is input as a part of the row address signals, it is not possible to select the memory cell arrays 100.about.130 by the column decoder 104. Therefore, even when the sense amplifiers 103, 113, 123 and 133 hold data, high speed access cannot be performed.
As discussed above, in the prior art, capability of high speed access is limited to one of a plurality of memory cell arrays 100.about.130. Therefore, there is a limitation for high speed access to the data held in the DRAM.